Electronic devices, such as a television and a personal computer, need power-supply devices that convert input voltage to output voltage optimum for components used in the electronic devices, such as converting AC power to DC power and converting voltage levels of DC power. For this reason, switching power supplies, which have high conversion efficiency, have been widely used conventionally.
A switching power supply is constituted by a switching device, such as a MOSFET and an IGBT, a transformer, and a capacitor, and the like and, by on/off control ng the switching device, converts voltage.
A control circuit that on/off controls a switching device is generally integrated into an integrated circuit (TC) Although the control circuit performs operation processing at a low voltage (for example, 1.8 V to 5.0 V) in order to reduce power consumption, driving a switching device, which is connected to an output of the control circuit, requires high voltage. For this reason, a driver circuit for a switching device has a level shift circuit that converts low power supply voltage in the control circuit to high power supply voltage (for example, 10 V to 60) for driving the switching device. Since the high power supply voltage (hereinafter, referred to as “VCC”) for driving varies depending on use, it is preferable that the driver circuit be capable of coping with a wide range of power supply voltage.
FIG. 5 is a diagram illustrative of an example of a conventional driver circuit including a level shift circuit (see, for example, FIG. 1 in JP 9-214317 A). FIGS. 6, 7, and 8 and 9 are a diagram illustrative of an example of a boost converter, a diagram illustrative of a circuit portion that is a portion extracted from the circuit in FIG. 5, and timing diagrams illustrative of switching operation of the circuit portion illustrated in FIG. 7, respectively.
As illustrated in FIG. 5, a driver circuit 200 includes a level shift circuit 130 and an output buffer circuit 50. To the driver circuit 200, a boost converter 60 is connected as an example of an object to be driven.
As illustrated in FIG. 6, the boost converter 60 includes an input power supply 61, a boost inductor 62, an N-channel type MOSFET 63, a boost diode 64, and a stabilizing capacitor 65. Hereinafter, an N-channel type MOSFET is abbreviated as an “NMOSFET”.
The boost converter 60 stores energy in the boost inductor 62 during an ON period of the NMOSFET 63 and supplies the stabilizing capacitor 65 with the stored energy via the boost diode 64 during an OFF period of the NMOSFET 63. This operation causes energy to be supplied to a load 66 via the stabilizing capacitor 65.
That is, the driver circuit 200 has its output terminal connected to the gate of the NMOSFET 63 in the boost converter 60 and serves as a circuit that drives the NMOSFET 63 serving as a switching device described above.
Returning to FIG. 5, the level shift circuit 130 includes a narrowly defined flip-flop circuit FF of a low power consumption type, variable resistance circuits (drain current variable circuits) 32 and 33, Zener diodes 34 and 35 for voltage clamping, and a CMOS inverter 36. In addition, the level shift circuit 130 includes one-shot circuits (monostable multivibrators) 23 and 24. The narrowly defined flip-flop circuit FF and the variable resistance circuits (drain current variable circuits) 32 and 33 constitute a broadly defined flip-flop circuit with the gate terminals of NMOSFETs 19 and 26 used as a set terminal and a reset terminal, respectively.
The flip-flop circuit FF includes a P-channel type MOSFET 18 that is on/off controlled by a signal S3 of a high voltage power supply system (hereinafter, referred to as a “high voltage system”) and a P-channel type MOSFET 25 that is on/off controlled exclusively from a MOSFET 3 by a signal S11 of the high voltage system. Hereinafter, a P-channel type MOSFET is abbreviated as a “PMOSFET”.
The PMOSFETs 19 and 25 constitute feedback loops with each other via drain nodes (memory nodes) N1 and N2. Specifically, the drain node N1 of the PMOSFET 18 is connected to the gate of the PMOSFET 25 and the drain node N2 of the PMOSFET 25 is connected to the gate of the PMOSFET 18. The PMOSFETs 19 and 25 have the sources electrically connected directly to an output terminal on the high potential side of a VCC power supply of the high voltage system, and the PMOSFETs 18 and 25 have the gates (drain nodes N1 and N2) thereof electrically connected, via the Zener diodes 34 and 35, to the output terminal on the high potential side of the VCC power supply. By setting Zener voltage Vz of the Zener diodes 34 and 35 at less than or equal to a breakdown voltage value of the PMOSFETs 18 and 25, voltage at the drain node N1 does not decrease to less than or equal to “VCC−Vz” because of voltage clamping by the Zener diode 35 even when the NMOSFET 19 turns on. Similarly, voltage at the drain node N2 does not decrease to less than or equal to “VCC−Vz” because of voltage clamping by the Zener diode 34 even when the NMOSFET 26 turns on.
The variable resistance circuit 32 includes the NMOSFET 19 having a high breakdown voltage, series-connected resistors 21 and 22 constituting a source follower circuit in conjunction with the NMOSFET 19, which operates in the non-saturation region, and an NMOSFET 20 for switching source resistance values that shunts the resistor 22, one of the series-connected resistors 21 and 22. Further, to the gate of the MOSFET 20, the output terminal of the one-shot circuit 23 is connected. The one-shot circuit 23 is a circuit that outputs a switching timing pulse signal S5 having a predetermined pulse width ΔT1 at a time point t1 at which a logic input signal S4, which is generated by a 5-V power supply of a low voltage power supply system (hereinafter, referred to as a “low voltage system”) and has voltage of the low voltage system (for example, 0 to 5 V), rises. Therefore, at the time point t1, at which the logic input signal S4 rises, the switching timing pulse signal S5 is applied to the gate of the NMOSFET 20.
Because of the configuration described above, at the time point t1 in a state transition process of the flip-flop circuit FF at which the logic input signal S4 of the low voltage system, input from a control circuit 300, rises, the NMOSFET 19 turns on and, in conjunction therewith, generation of the switching timing pulse signal S5 causes the NMOSFET 20 to be maintained in the ON state only during a period of ΔT1. Since, for this reason, only the resistor 21 constitutes the source resistor of the NMOSFET 19, drain current ID1 flowing through the NMOSFET 19 increases to a large value. However, since, after the period of ΔT1 has elapsed, the NMOSFET 20 turns off and the resistor 22 is thereby connected in series to the resistor 21, the drain current ID1 flowing through the NMOSFET 19 rapidly decreases to a minute current sufficient to maintain conduction of the Zener diode 35.
The variable resistance circuit 33 includes the NMOSFET 26 having a high breakdown voltage, series-connected resistors 28 and 29 constituting a source follower circuit in conjunction with the NMOSFET 26, which operates in the non-saturation region, and an NMOSFET 27 for switching source resistance values that shunts the resistor 29, one of the series-connected resistors 28 and 29. Further, to the gate of the NMOSFET 27, the output terminal of the one-shot circuit 24 is connected. The one-shot circuit 24 is a circuit that outputs a switching timing pulse signal S10 having a predetermined pulse width ΔT2 at a time point t2 at which the logic input signal S4 falls. Therefore, at the time point t2, at which the logic input signal S4 falls, the switching timing pulse signal S10 is applied to the gate of the NMOSFET 27.
Because of the configuration described above, at the time point t2 in another state transition process at which the logic input signal S4 falls, the NMOSFET 26 turns on and, in conjunction therewith, generation of the switching timing pulse signal S10 causes the NMOSFET 27 to be maintained in the ON state only during a period of ΔT2. Since, for this reason, only the resistor 28 constitutes the source resistor of the NMOSFET 26, drain current ID2 flowing through the NMOSFET 26 increases to a large value. However, since, after the period of ΔT2 has elapsed, the NMOSFET 27 turns off and the resistor 29 is thereby connected in series to the resistor 28, the drain current ID2 flowing through the NMOSFET 26 rapidly decreases to a minute current sufficient to maintain conduction of the Zener diode 34.
Since, as described above, the drain current ID1 and ID2 of the NMOSFETs 19 and 26 rapidly increase in the transition processes of the flip-flop circuit FF and become minute current while the flip-flop circuit FF is in a stable state, the drain current ID1 and ID2 contribute to secure execution of state transition and reduction in power consumption. Hereinafter, drain current at the time of rapid increase is referred to as “rapidly increasing current”.
The CMOS inverter 36 generates, from the logic input signal S4, an inverted signal S2 of the low voltage system (for example, 5 V) that has a reverse phase to that of the logic input signal S4 and applies the generated signal S2 to the gate of an NMOSFET 1, the gate of the NMOSFET 26, and the input terminal of the one-shot circuit 24.
The output buffer circuit 50 includes the NMOSFET 1 and a PMOSFET 2 at an output stage, a Zener diode 6, a gate capacitance discharge circuit 51 that rapidly discharges gate capacitance C3 of the output stage PMOSFET 2 on the occasion when the flip-flop circuit FF transitions to one state, and a gate capacitance charging circuit 52 that rapidly charges the gate capacitance C3 of the output stage PMOSFET 2 on the occasion when the flip-flop circuit FF transitions to the other state.
The NMOSFET 1 has the source, drain, and gate thereof electrically connected to ground, the drain of the PMOSFET 2, and the output terminal of the inverter 36, respectively. The PMOSFET 2 has the source and gate thereof electrically connected to an output terminal on the high potential side of the VCC power supply and the drain of the PMOSFET 3, respectively. Further, between the gate of the PMOSFET 2 and the output terminal on the high potential side of the VCC power supply, the Zener diode 6 for voltage clamping is connected.
The gate capacitance discharge circuit 51 is a circuit that extracts charges from the gate, having the gate capacitance C3, of the PMOSFET 2 and supplies the extracted charges to ground and thereby decreases voltage at the gate. The gate capacitance discharge circuit 51 includes a high breakdown voltage NMOSFET 4 that is on/off controlled in synchronization with the NMOSFET 19 by the logic input signal S4, series-connected resistors 7 and 8 constituting a source follower circuit (constant current circuit) in conjunction with the NMOSFET 4, which operates in the non-saturation region, and an NMOSFET 5 for switching source resistance values that shunts the resistor 8, one of the series-connected resistors 7 and 8. The NMOSFET 5 receives the timing pulse signal S5 from the one-shot circuit 23 and is on/off controlled by the timing pulse signal S5.
Although being named differently due to differences in roles, the gate capacitance discharge circuit 51 can be said to be a variable resistance circuit because of having a similar circuit configuration to those of the variable resistance circuits 32 and 33.
The gate capacitance charging circuit 52 includes the PMOSFET 3 that is a comparatively large element, is connected across the gate capacitance C3, and is on/off controlled by node voltage (signal S3) at the drain node N2. Between the gate of the PMOSFET 3 and the output terminal on the high potential side of the VCC power supply, the Zener diode 34 for voltage clamping is connected.
Meanwhile, a circuit portion illustrated in FIG. 7 that is extracted from the driver circuit 200 having the above-described configuration is configured including the NMOSFETs 1, 4, and 5, the PMOSFETs 2 and 3, the resistors 7 and 8, and the Zener diode 6. VOUT (logic output signal) in FIG. 7 is an output of the driver circuit 200 that is output via the PMOSFET 2 at the output stage and is connected to the gate of the NMOSFET 63 of the boost converter 60 in the circuit example illustrated in FIGS. 5 and 6.
Hereinafter, operation of the circuit portion illustrated in FIG. 7 will be described.
In the circuit portion, as illustrated in a timing diagram in FIG. 8, when the signal S2 turns to a high level (5 V) and the NMOSFET 1 thereby turns on and a signal S1 turns to a high level (VCC) and the PMOSFET 2 thereby turns off, a signal of a low level (0 V) is output as VOUT. When the signal S2 turns to a low level (0 V) and the NMOSFET 1 thereby turns off and the signal S1 turns to a low level (VCC-5 V) and the PMOSFET 2 thereby turns on, a signal of a high level (VCC) is output as VOUT.
Although having a high breakdown voltage of 10 V or more with respect to drain-source voltage (hereinafter, referred to as “Vds”), the NMOSFET 1 and the PMOSFET 2 have a low breakdown voltage of 5 V with respect to gate-source voltage (hereinafter, referred to as “Vgs”). Thus, the signals S1 and S2 serve as drive signals in a range from VCC to VCC-5 V and a range from 0 V to 5 V, respectively. The signal S1 driving the PMOSFET 2 is generated in accordance with a timing diagram in FIG. 9. That is, the signal S1 is at the high level when the signals S3 and S4 are at low levels. The signal S5 in FIG. 9 is a one-shot pulse signal that is a signal that rises only for a period of ΔT1 in response to a rise of the signal S4.
When the PMOSFET 2 turns from the OFF state to the ON state, by turning on the NMOSFETs 4 and 5 at the same time only for a short transition period (the period of ΔT1) in which the signal S1 turns from the high level (VCC) to the low level (VCC-5 V), the gate of the PMOSFET 2 is pulled down by the resistor 7.
Specifically, when the signal S1 transitions from the high level to the low level, the signal S4 is turned to a high level and, in conjunction therewith, the signal S5 is turned to a high level (5 V) only for the transition period. Subsequently, when the signal S5 turns to a low level, the NMOSFET 5 turns off and only the NMOSFET 4 maintains the ON state, which causes the PMOSFET 2 to maintain the ON state with an impedance of the series connection of the resistors 7 and 8. On this occasion, a resistor having a low resistance is selected as the resistor 7 in order to extract charges accumulated at the gate of the PMOSFET 2 in a short period of time, and a resistor having a high resistance is selected as the resistor 8 in order to reduce current consumption. This configuration enables the switching device (NMOSFET 63) to be driven with small power consumption. In addition, the source-gate voltage of the PMOSFET 2 is clamped by the Zener diode 6 lest Vgs exceeds a gate breakdown voltage when the gate of the PMOSFET 2 is pulled down.